A MAJORITY FUNCTION BASED APPROACH TO REDUCE LEAKAGE BY REDUCING NUMBER OF TRANSISTORS IN CMOS LOGIC GATES

Angshuman Chakraborty

Abstract


There has always been a continuous urge to reduce power consumption in VLSI circuit design. But, there stands a tradeoff in between power, delay and size of the chip. Static and dynamic power gets escalated as the device dimension is scaled down and vice versa. In our approach, we aim at the reduction of power and delay by altering the generalized structure of conventional universal gates.


Keywords


VLSI, Leakage power, stacking, Majority function, Universal gate

References


R.M. Rao, F. Liu, J.L. Burns and R.B. Brown,”A heuristic to determine low leakage sleep state vectors for CMOS combinational circuits”, in proceedings of ICCAD, pp. 689–692, 2003.

C. Choi, K. Nam, Z.Y u and R. Dutton, “Impact of gate direct tunneling current on circuit performance: A simulation study”, in IEEE transaction on electron device,Vol. 48, No.12, pp. 2823-

, 2001.

G. Yang, William N.H. Hung, X. Song and M. Perkowski, “Majority based reversible logic gates”, in theotrical computer science (Elsevier), pp. 259-274, 2005.

R.M. Rao, J. L. Burns, A. Devgan and R. B. Brown, “Efficient Techniques for Gate Leakage Estimation”, in proceedings of ISLPED, pp.100-103, 2003.

S.F. Hsiao, M.Y. Tsai and C.S. Wen, “Low area/power synthesis using hybrid pass transistor/CMOS logic cells in standard cell-based design environment”, in IEEE transactions on circuits and systems ii, Vol. 57, No. 1, pp. 21–25, 2010.

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DOI: https://doi.org/10.37591/rrjophy.v12i3.3816

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