An Approach to Simplify Universal Logic Gates Using Majority Function

Authors

  • Angshuman Chakraborty Tripura Institute of Technology, Tripura

DOI:

https://doi.org/10.37591/rrjophy.v12i3.3816

Keywords:

VLSI, Leakage power, stacking, Majority function, Universal gate

Abstract

There has always been a continuous urge to reduce power consumption in very large scale integration (VLSI) circuit design. Sometimes reduction in the total number of transistors in a fundamental logic gate helps to enhance power saving. But, there stands a tradeoff in between power, delay and size of the chip. Static and dynamic power gets escalated as the device dimension is scaled down and vice versa. In our approach, I aim at the reduction of power and delay by altering the generalized structure of conventional universal gates. This in turn will help to integrate more functions per unit area. Whole of the concept of transistor reduction is based around “Majority Function”. In general, majority gate is nothing but a logical gate that are being used in circuit complexity as well as in other applications of Boolean based circuits. A majority gate returns true if and only if more than 50% of its inputs are true. Any improvisation in the performance of these gates modified with majority function will lead to efficient corresponding change in VLSI logic device performance.

Author Biography

Angshuman Chakraborty, Tripura Institute of Technology, Tripura

Department of ECE

References

R.M. Rao, F. Liu, J.L. Burns and R.B. Brown,”A heuristic to determine low leakage sleep state vectors for CMOS combinational circuits”, in proceedings of ICCAD, pp. 689–692, 2003.

C. Choi, K. Nam, Z.Y u and R. Dutton, “Impact of gate direct tunneling current on circuit performance: A simulation study”, in IEEE transaction on electron device,Vol. 48, No.12, pp. 2823-

, 2001.

G. Yang, William N.H. Hung, X. Song and M. Perkowski, “Majority based reversible logic gates”, in theotrical computer science (Elsevier), pp. 259-274, 2005.

R.M. Rao, J. L. Burns, A. Devgan and R. B. Brown, “Efficient Techniques for Gate Leakage Estimation”, in proceedings of ISLPED, pp.100-103, 2003.

S.F. Hsiao, M.Y. Tsai and C.S. Wen, “Low area/power synthesis using hybrid pass transistor/CMOS logic cells in standard cell-based design environment”, in IEEE transactions on circuits and systems ii, Vol. 57, No. 1, pp. 21–25, 2010.

http://ptm.asu.edu

Downloads

Published

2024-03-30

Issue

Vol. 12 No. 3 (2023)

Section

Research Article

License

Declaration and Copyright Transfer Form

(to be completed by authors)

I/ We, the undersigned author(s) of the submitted manuscript, hereby declare, that the above manuscript which is submitted for publication in the STM Journals(s), is not published already in part or whole (except in the form of abstract) in any journal or magazine for private or public circulation, and, is not under consideration of publication elsewhere.

  • I/We will not withdraw the manuscript after 1 week of submission as I have read the Author Guidelines and will adhere to the guidelines.
  • I/We Author(s ) have niether given nor will give this manuscript elsewhere for publishing after submitting in STM Journal(s).
  • I/ We have read the original version of the manuscript and am/ are responsible for the thought contents embodied in it. The work dealt in the manuscript is my/ our own, and my/ our individual contribution to this work is significant enough to qualify for authorship.
  •  I/We also agree to the authorship of the article in the following order:

Author’s name                                    

 

1. ________________

2. ________________

3. ________________

4. ________________

 

We  Author(s) tick this box and would request you to consider it as our signature as we agree to the terms of this Copyright Notice, which will apply to this submission if and when it is published by this journal.