A MAJORITY FUNCTION BASED APPROACH TO REDUCE LEAKAGE BY REDUCING NUMBER OF TRANSISTORS IN CMOS LOGIC GATES
Abstract
There has always been a continuous urge to reduce power consumption in VLSI circuit design. But, there stands a tradeoff in between power, delay and size of the chip. Static and dynamic power gets escalated as the device dimension is scaled down and vice versa. In our approach, we aim at the reduction of power and delay by altering the generalized structure of conventional universal gates.
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References
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DOI: https://doi.org/10.37591/rrjophy.v12i3.3816
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